1. Field of the Invention
The present invention relates generally to a semiconductor device, and more particularly, to a semiconductor device having an alignment mark which is detected by laser beam.
2. Description of the Background Art
FIG. 7 is a plan view of a wafer. A plurality of chips 41 are formed on wafer 40. FIG. 8 is a plan view of a chip. A semiconductor device (not shown) is formed on chip 41. A plurality of alignment marks 42, which will be described later, are usually formed on chip 41.
Functions of the alignment marks 42 will now be described.
A semiconductor device, in particular, a semiconductor memory device has a spare portion therein. If a portion of a circuit of the semiconductor memory device is found to be defective, the defective portion is separated from a main portion by cutoff of a particular portion of an interconnection, and the defective portion is replaced with the above-described spare portion. A defective portion is found by a test equipment, and coordinates of an interconnection to be cut off are calculated. Laser beam is directed to the interconnection which is located on the calculated coordinates, whereby the interconnection is cut off. A laser trimmer (an apparatus for carrying out the above-described operation) has functions of directing laser beam with an arbitrary intensity to an arbitrary portion of chip 41 and of measuring intensity of the directed laser beam reflected from a chip surface. The laser trimmer recognizes alignment mark 42 provided on each chip 41, of which coordinates are known in advance, and moves a laser source to a position where an interconnection should be cut off, based on the coordinates of this alignment mark 42. When the location is determined, laser beam is directed thereto, and the interconnection is cut out.
FIG. 9 is a plan view of a portion of a conventional semiconductor device, where an alignment mark exists. FIG. 10 is a cross section taken along line X--X shown in FIG. 9.
Referring to these figures, a first interlayer insulating film 6a is provided on a semiconductor substrate 5. A first interconnection layer 12 made of a low reflectance material (for example, polysilicon) is provided on first interlayer insulating film 6a. A second interlayer insulating film 6b is provided on first interlayer insulating film 6a so that it covers first interconnection layer 12. A second interconnection layer 11 is provided on first interlayer insulating film 6a, so that first and second interconnection layers 12 and 11 cross each other with second interlayer insulating film 6b therebetween. Second interconnection layer 11 is formed of a high reflectance material (for example, A1 interconnection). In a semiconductor device with a multi-layer interconnection structure, the second interconnection layer is the uppermost interconnection layer, and is a power supply interconnection.
Second interconnection layer 11 is provided with an L-shaped opening 11a and a rectangular opening 11b, when viewed two-dimensionally, in a region where first and second interconnection layers 12 and 11 cross each other. Thus, an alignment mark is formed. Use of such a connected portion for an alignment mark eliminates the need to form an alignment mark separately.
Operation will now be described. The laser trimmer directs a laser beam to the approximate location where the alignment mark exists, for example, from point a to point b of FIG. 9 (hereinafter represented by a-b). The intensity of reflected light at each point between a-b is measured. FIG. 12 is a graph showing intensity of reflected light at each point between a-b of FIG. 9. Referring to FIGS. 9, 11 and 12, when laser beam 43 is directed to a-c or d-b, laser beam 43 passes through second interlayer insulating film 6b, and then is reflected from first interconnection layer 12 which is made of a low reflectance material. Since second interconnection layer 12 is made of a low reflectance material, the intensity of reflected light is low. On the other hand, when laser beam 43 is directed to c-d, the intensity of reflected light is high, since laser beam 43 is reflected from second interconnection layer 11 which is made of a high reflectance material. From the resulting data shown in FIG. 12, the laser trimmer recognizes an intermediate point M of the portion c-d in which reflected light intensity is high as the central point e of an alignment mark which has been provided in advance on the chip. Although M and e are not located on the same line in the graph for convenience, they correspond with each other.
In a conventional semiconductor device having an alignment mark, the central point e of the alignment mark is obtained based on the difference in reflected light intensity between any two portions between a-c, d-b and c-d, as described above. The difference in reflected light intensity depends on the difference in reflectance between two materials (i.e. first and second interconnection layers 12 and 11). Therefore, the following problems arise, if an interconnection, made of material of which reflectance is close to that of the material which forms the alignment mark, is provided under the alignment mark.
That is, if the difference in reflectance between two materials is not sufficient, or if the surface of the mark is contaminated, reflected light intensity becomes unstable as shown by curve F in FIG. 13. In such a case, the central point of the region with high intensity of the reflected light, which is recognized as the center of the alignment mark by the laser trimmer might be largely deviated from the actual central point of the alignment mark.
In addition, since the above-described two materials (i.e. first and second interconnections) must be those which form a main body of a semiconductor device, those materials cannot be selected arbitrarily.
Moreover, when an alignment mark is formed on an interconnection as in the above-described conventional example, since the shape of the interconnection is changed into that of the alignment mark, a portion of the interconnection becomes thin, and electric resistance increases at the portion, resulting in degradation of property of a semiconductor device.